The integrated circuit (IC) design is more challenging when semiconductor technologies are continually progressing to smaller feature sizes, such as 65 nanometers, 45 nanometers, and below. The performance of a chip design is seriously influenced by the control of resistance/capacitance (RC), timing, leakage, and topology of the metal/dielectric inter-layers. In the semiconductor fabrication, various processing-modules are involved. Each module releases some representative information to design model for the follow-up works. Afterward, a statistical corner is added onto the simulation model for design reference. Such design flow lacks of cross-team interaction, especially when the feature size is dramatically shrunken in upcoming advanced technologies. The existing design method is challenged by various problems. For example, every module in current semiconductor processing modeling, such as lithography patterning, thin film deposition, etching and etc, is independent from other modules. The full chip tape, as the final design product, cannot be achieved without maximized modeling efficiency. In another problem, the statistical corner used for design reference reduces the design flexibility and design margin. Furthermore, in the current IC design flow, the patterns used in the simulation are too simpler than the frequently designed patterns. Therefore, what is needed is a method and a system to provide effective IC design for the advanced IC technologies addressing the above problems.